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authorBen Skeggs <bskeggs@redhat.com>2012-09-27 08:55:53 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-10-03 13:13:17 +1000
commite5f186c4f9812eccbc291da6dfe8b15da546f961 (patch)
tree84e667ebbe00bd91e10cff16defaad95b38d85a9 /drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h
parent8a57d279d6e1bf19d2d2e54f51d4f40c46c7d1a8 (diff)
downloadop-kernel-dev-e5f186c4f9812eccbc291da6dfe8b15da546f961.zip
op-kernel-dev-e5f186c4f9812eccbc291da6dfe8b15da546f961.tar.gz
drm/nv44/vm: fix and enable use of "real" pciegart
Something seems to be missing in regards to flushing specific ranges of the TLB. For the moment, flushing the entire thing seems to make it work alright. Should give 39-bit DMA addressing on the relevant chipsets. v2: allocate contig 16KiB for dummy pages, reported by mwk on irc Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h')
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h
index e21369c..ec42d4b 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h
@@ -6,8 +6,8 @@
struct nv04_vmmgr_priv {
struct nouveau_vmmgr base;
struct nouveau_vm *vm;
- struct page *page;
dma_addr_t null;
+ void *nullp;
};
static inline struct nv04_vmmgr_priv *
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