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| author | Ben Skeggs <bskeggs@redhat.com> | 2014-06-12 18:58:05 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-10 05:11:06 +1000 |
| commit | 61854bdb135d1b958a5057739206d663528870db (patch) | |
| tree | 9b49ee52cb34bb4587120a91e78a4bce37f9f9b4 /drivers/gpu/drm/nouveau/core/include/subdev | |
| parent | adec9bc3bd5f2618cea5ab8dccc506b86ab4aabb (diff) | |
| download | op-kernel-dev-61854bdb135d1b958a5057739206d663528870db.zip op-kernel-dev-61854bdb135d1b958a5057739206d663528870db.tar.gz | |
drm/gk104/pwr: implement PGOB disable method
As documented at:
ftp://download.nvidia.com/open-gpu-doc/gk104-disable-graphics-power-gating/1/gk104-disable-graphics-power-gating.txt
NVIDIA were not able document the steps necessary to detect whether this
is required or not at this time. However, they did confirm that this
procedure is safe to perform unconditionally on GK104/6. GK107 does not
have the power gating feature, and it was recommended that we do not
perform these steps there as the effects were not verified.
The disable path is from observing the binary driver, and not
documented in the link above.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/include/subdev')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/include/subdev/pwr.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h index edf1118..f73feec 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h @@ -23,7 +23,8 @@ struct nouveau_pwr { u32 data[2]; } recv; - int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32); + int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32); + void (*pgob)(struct nouveau_pwr *, bool); }; static inline struct nouveau_pwr * @@ -35,6 +36,7 @@ nouveau_pwr(void *obj) extern struct nouveau_oclass *nva3_pwr_oclass; extern struct nouveau_oclass *nvc0_pwr_oclass; extern struct nouveau_oclass *nvd0_pwr_oclass; +extern struct nouveau_oclass *gk104_pwr_oclass; extern struct nouveau_oclass *nv108_pwr_oclass; /* interface to MEMX process running on PPWR */ |
