diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2013-05-13 18:29:02 +1000 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2013-07-01 13:50:40 +1000 |
commit | 58ef23056ae0bc060086f71ad04254e188a30ff0 (patch) | |
tree | e7f95debc473ab3ef691dd40f1149931ea90d5a2 /drivers/gpu/drm/nouveau/core/engine | |
parent | 8b637ae3a3d8142db23eed3100245c2a2390358b (diff) | |
download | op-kernel-dev-58ef23056ae0bc060086f71ad04254e188a30ff0.zip op-kernel-dev-58ef23056ae0bc060086f71ad04254e188a30ff0.tar.gz |
drm/nvc1/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine')
6 files changed, 80 insertions, 35 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c index 27e97c0..f98d087 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c @@ -1327,6 +1327,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: case 0xc3: + case 0xc1: case 0xd9: case 0xd7: break; @@ -1475,6 +1476,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -1496,6 +1498,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x4040d0, 0x00000000); @@ -1524,6 +1527,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x404174, 0x00000000); break; @@ -1709,6 +1713,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -1771,7 +1776,6 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x408900, 0x3080b801); nv_wr32(priv, 0x408904, 0x62000001); nv_wr32(priv, 0x408908, 0x00c80929); - nv_wr32(priv, 0x40890c, 0x00000000); break; case 0xd9: case 0xd7: @@ -1806,6 +1810,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418408, 0x00000000); break; @@ -1819,6 +1824,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418414, 0x00200fff); break; @@ -1844,6 +1850,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x41870c, 0x07c80000); break; @@ -1856,6 +1863,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418800, 0x0006860a); break; @@ -1917,6 +1925,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418b00, 0x00000000); break; @@ -1986,6 +1995,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) case 0xc0: break; case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x419a1c, 0x00000000); nv_wr32(priv, 0x419a20, 0x00000800); @@ -2000,6 +2010,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x00419ac4, 0x0017f440); break; case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x00419ac4, 0x0007f440); break; @@ -2031,6 +2042,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x419c00, 0x00000002); break; @@ -2040,6 +2052,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419c20, 0x00000000); switch (nv_device(priv)->chipset) { case 0xc3: + case 0xc1: case 0xce: case 0xcf: nv_wr32(priv, 0x419cb0, 0x00020048); @@ -2115,6 +2128,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419ee0, 0x00010110); break; case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x419ee0, 0x00011110); break; @@ -2126,6 +2140,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419f54, 0x00000000); break; case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x419f30, 0x00000000); @@ -2463,6 +2478,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -2482,6 +2498,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: break; default: break; @@ -3049,11 +3066,13 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x00000585, 0x0000003f); nv_icmd(priv, 0x00000576, 0x00000003); switch (nv_device(priv)->chipset) { + case 0xc1: case 0xd9: case 0xd7: nv_icmd(priv, 0x0000057b, 0x00000059); break; case 0xc0: + case 0xc3: default: break; } @@ -3163,6 +3182,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x0000097d, 0x00000020); break; case 0xc0: + case 0xc3: + case 0xc1: default: break; } @@ -3311,6 +3332,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: case 0xc3: + case 0xc1: nv_mthd(priv, 0x902d, 0x3410, 0x00000000); break; case 0xd9: diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc index f9874a5..79a3a50 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc @@ -53,10 +53,10 @@ chipsets: .b16 #nnvc0_tpc_mmio_head .b16 #nnvc0_tpc_mmio_tail .b8 0xc1 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc1_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc1_tpc_mmio_tail +.b16 #nnvc0_gpc_mmio_head +.b16 #nnvc1_gpc_mmio_tail +.b16 #nnvc3_tpc_mmio_head +.b16 #nnvc1_tpc_mmio_tail .b8 0xc3 0 0 0 .b16 #nnvc0_gpc_mmio_head .b16 #nnvc0_gpc_mmio_tail @@ -121,8 +121,6 @@ mmctx_data(0x000c8c, 1) mmctx_data(0x001000, 3) mmctx_data(0x001014, 1) nvc0_gpc_mmio_tail: -mmctx_data(0x000c6c, 1); -nvc1_gpc_mmio_tail: nnvc0_gpc_mmio_head: mmctx_data(0x000380, 1) @@ -150,6 +148,8 @@ mmctx_data(0x000c8c, 1) mmctx_data(0x001000, 3) mmctx_data(0x001014, 1) nnvc0_gpc_mmio_tail: +mmctx_data(0x000c6c, 1); +nnvc1_gpc_mmio_tail: nvd9_gpc_mmio_head: mmctx_data(0x000380, 1) @@ -209,8 +209,6 @@ mmctx_data(0x0006e0, 1) nvcf_tpc_mmio_tail: mmctx_data(0x0004bc, 1) nvc3_tpc_mmio_tail: -mmctx_data(0x000544, 1) -nvc1_tpc_mmio_tail: nnvc0_tpc_mmio_head: mmctx_data(0x000018, 1) @@ -258,6 +256,8 @@ mmctx_data(0x000698, 1) mmctx_data(0x0006e0, 1) mmctx_data(0x000730, 11) nnvc3_tpc_mmio_tail: +mmctx_data(0x000544, 1) +nnvc1_tpc_mmio_tail: nvd9_tpc_mmio_head: mmctx_data(0x000018, 1) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index 0db0481..1a16cbf 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h @@ -34,14 +34,14 @@ uint32_t nvc0_grgpc_data[] = { 0x00000000, /* 0x0064: chipsets */ 0x000000c0, - 0x01980138, - 0x02b00264, + 0x01940134, + 0x02ac0260, 0x000000c1, - 0x013800d4, - 0x02640200, + 0x01980134, + 0x030802ac, 0x000000c3, - 0x01980138, - 0x030802b0, + 0x01940134, + 0x030402ac, 0x000000c4, 0x013400d4, 0x02600200, @@ -87,9 +87,7 @@ uint32_t nvc0_grgpc_data[] = { 0x08001000, 0x00001014, /* 0x0134: nvc0_gpc_mmio_tail */ - 0x00000c6c, -/* 0x0138: nvc1_gpc_mmio_tail */ -/* 0x0138: nnvc0_gpc_mmio_head */ +/* 0x0134: nnvc0_gpc_mmio_head */ 0x00000380, 0x14000400, 0x20000450, @@ -114,7 +112,9 @@ uint32_t nvc0_grgpc_data[] = { 0x00000c8c, 0x08001000, 0x00001014, -/* 0x0198: nnvc0_gpc_mmio_tail */ +/* 0x0194: nnvc0_gpc_mmio_tail */ + 0x00000c6c, +/* 0x0198: nnvc1_gpc_mmio_tail */ /* 0x0198: nvd9_gpc_mmio_head */ 0x00000380, 0x04000400, @@ -171,9 +171,7 @@ uint32_t nvc0_grgpc_data[] = { /* 0x025c: nvcf_tpc_mmio_tail */ 0x000004bc, /* 0x0260: nvc3_tpc_mmio_tail */ - 0x00000544, -/* 0x0264: nvc1_tpc_mmio_tail */ -/* 0x0264: nnvc0_tpc_mmio_head */ +/* 0x0260: nnvc0_tpc_mmio_head */ 0x00000018, 0x0000003c, 0x00000048, @@ -193,8 +191,8 @@ uint32_t nvc0_grgpc_data[] = { 0x4c000644, 0x00000698, 0x04000750, -/* 0x02b0: nnvc0_tpc_mmio_tail */ -/* 0x02b0: nnvc3_tpc_mmio_head */ +/* 0x02ac: nnvc0_tpc_mmio_tail */ +/* 0x02ac: nnvc3_tpc_mmio_head */ 0x00000018, 0x0000003c, 0x00000048, @@ -217,7 +215,9 @@ uint32_t nvc0_grgpc_data[] = { 0x00000698, 0x000006e0, 0x28000730, -/* 0x0308: nnvc3_tpc_mmio_tail */ +/* 0x0304: nnvc3_tpc_mmio_tail */ + 0x00000544, +/* 0x0308: nnvc1_tpc_mmio_tail */ /* 0x0308: nvd9_tpc_mmio_head */ 0x00000018, 0x0000003c, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc index 58e8d01..5305b09 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc @@ -51,7 +51,7 @@ chipsets: .b16 #nnvc0_hub_mmio_head .b16 #nnvc0_hub_mmio_tail .b8 0xc1 0 0 0 -.b16 #nvc0_hub_mmio_head +.b16 #nnvc0_hub_mmio_head .b16 #nvc1_hub_mmio_tail .b8 0xc3 0 0 0 .b16 #nnvc0_hub_mmio_head @@ -117,8 +117,6 @@ mmctx_data(0x408800, 3) mmctx_data(0x408900, 4) mmctx_data(0x408980, 1) nvc0_hub_mmio_tail: -mmctx_data(0x4064c0, 2) -nvc1_hub_mmio_tail: nnvc0_hub_mmio_head: mmctx_data(0x17e91c, 2) @@ -161,6 +159,8 @@ mmctx_data(0x408800, 3) mmctx_data(0x408900, 3) mmctx_data(0x408980, 1) nnvc0_hub_mmio_tail: +mmctx_data(0x4064c0, 2) +nvc1_hub_mmio_tail: nvd9_hub_mmio_head: mmctx_data(0x17e91c, 2) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h index 6466bcf..1cdf9e9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h @@ -203,11 +203,11 @@ uint32_t nvc0_grhub_data[] = { 0x00000000, /* 0x0300: chipsets */ 0x000000c0, - 0x048803ec, + 0x048403e8, 0x000000c1, - 0x03ec034c, + 0x048803e8, 0x000000c3, - 0x048803ec, + 0x048403e8, 0x000000c4, 0x03e8034c, 0x000000c8, @@ -262,9 +262,7 @@ uint32_t nvc0_grhub_data[] = { 0x0c408900, 0x00408980, /* 0x03e8: nvc0_hub_mmio_tail */ - 0x044064c0, -/* 0x03ec: nvc1_hub_mmio_tail */ -/* 0x03ec: nnvc0_hub_mmio_head */ +/* 0x03e8: nnvc0_hub_mmio_head */ 0x0417e91c, 0x04400204, 0x28404004, @@ -304,7 +302,9 @@ uint32_t nvc0_grhub_data[] = { 0x08408800, 0x08408900, 0x00408980, -/* 0x0488: nnvc0_hub_mmio_tail */ +/* 0x0484: nnvc0_hub_mmio_tail */ + 0x044064c0, +/* 0x0488: nvc1_hub_mmio_tail */ /* 0x0488: nvd9_hub_mmio_head */ 0x0417e91c, 0x04400204, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index 5f39dd2..18bcc34 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -754,6 +754,7 @@ nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -766,6 +767,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x405850, 0x00000000); switch (nv_device(priv)->chipset) { case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x405900, 0x00002834); @@ -783,6 +785,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -804,6 +807,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -816,6 +820,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -824,6 +829,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xd9: case 0xd7: + case 0xc1: nv_wr32(priv, 0x418714, 0x00000000); break; case 0xc0: @@ -840,6 +846,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xd9: case 0xd7: + case 0xc1: nv_wr32(priv, 0x4188c8, 0x00000000); break; case 0xc0: @@ -867,6 +874,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -879,6 +887,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -892,6 +901,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -901,6 +911,8 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) case 0xd7: nv_wr32(priv, 0x418f20, 0x00000000); nv_wr32(priv, 0x418f24, 0x00000000); + /*fall-through*/ + case 0xc1: nv_wr32(priv, 0x418e00, 0x00000003); break; case 0xc0: @@ -918,6 +930,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -934,6 +947,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419ab0, 0x00000000); switch (nv_device(priv)->chipset) { case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x419ac8, 0x00000000); @@ -953,6 +967,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x41980c, 0x00000000); break; @@ -961,6 +976,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xd9: case 0xd7: + case 0xc1: nv_wr32(priv, 0x419814, 0x00000004); break; case 0xc0: @@ -977,6 +993,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x41984c, 0x00005bc5); break; @@ -987,6 +1004,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x41985c, 0x00000000); switch (nv_device(priv)->chipset) { case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x419880, 0x00000002); @@ -1012,6 +1030,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -1024,6 +1043,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -1038,6 +1058,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x419ea8, 0x00001100); break; @@ -1050,6 +1071,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419ec0, 0x00000000); switch (nv_device(priv)->chipset) { case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x419ec8, 0x0e063818); @@ -1333,6 +1355,7 @@ nvc0_graph_init(struct nouveau_object *object) switch (nv_device(priv)->chipset) { case 0xc0: case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nvc0_graph_init_unk40xx(priv); |