diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-10-08 14:29:16 +1000 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-11-29 09:56:39 +1000 |
commit | f756944a219cb2d38b0859e8af680f9b216de1e3 (patch) | |
tree | 85bef8abe897bd9fd53c6f942978e6b9895491b6 /drivers/gpu/drm/nouveau/core/engine/dmaobj | |
parent | 344e107df7a5c365287aabe9df7df58b3765246b (diff) | |
download | op-kernel-dev-f756944a219cb2d38b0859e8af680f9b216de1e3.zip op-kernel-dev-f756944a219cb2d38b0859e8af680f9b216de1e3.tar.gz |
drm/nv50/dmaobj: extend class to allow gpu-specific attributes to be defined
disp is going to need to be able to create more specific dma objects
than was previously possible.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/dmaobj')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c | 43 |
2 files changed, 30 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c index 325b79d..5103e88 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c +++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c @@ -85,6 +85,7 @@ nouveau_dmaobj_ctor(struct nouveau_object *parent, dmaobj->start = args->start; dmaobj->limit = args->limit; + dmaobj->conf0 = args->conf0; switch (nv_mclass(parent)) { case NV_DEVICE_CLASS: diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c index 3dab016..bda7afc 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c @@ -38,7 +38,8 @@ nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng, struct nouveau_dmaobj *dmaobj, struct nouveau_gpuobj **pgpuobj) { - u32 flags = nv_mclass(dmaobj); + u32 flags0 = nv_mclass(dmaobj); + u32 flags5 = 0x00000000; int ret; if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { @@ -53,23 +54,37 @@ nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng, } } + if (!(dmaobj->conf0 & NV50_DMA_CONF0_ENABLE)) { + if (dmaobj->target == NV_MEM_TARGET_VM) { + dmaobj->conf0 = NV50_DMA_CONF0_PRIV_VM; + dmaobj->conf0 |= NV50_DMA_CONF0_PART_VM; + dmaobj->conf0 |= NV50_DMA_CONF0_COMP_VM; + dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_VM; + } else { + dmaobj->conf0 = NV50_DMA_CONF0_PRIV_US; + dmaobj->conf0 |= NV50_DMA_CONF0_PART_256; + dmaobj->conf0 |= NV50_DMA_CONF0_COMP_NONE; + dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_LINEAR; + } + } + + flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_COMP) << 22; + flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_TYPE) << 22; + flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_PRIV); + flags5 |= (dmaobj->conf0 & NV50_DMA_CONF0_PART); + switch (dmaobj->target) { case NV_MEM_TARGET_VM: - flags |= 0x00000000; - flags |= 0x60000000; /* COMPRESSION_USEVM */ - flags |= 0x1fc00000; /* STORAGE_TYPE_USEVM */ + flags0 |= 0x00000000; break; case NV_MEM_TARGET_VRAM: - flags |= 0x00010000; - flags |= 0x00100000; /* ACCESSUS_USER_SYSTEM */ + flags0 |= 0x00010000; break; case NV_MEM_TARGET_PCI: - flags |= 0x00020000; - flags |= 0x00100000; /* ACCESSUS_USER_SYSTEM */ + flags0 |= 0x00020000; break; case NV_MEM_TARGET_PCI_NOSNOOP: - flags |= 0x00030000; - flags |= 0x00100000; /* ACCESSUS_USER_SYSTEM */ + flags0 |= 0x00030000; break; default: return -EINVAL; @@ -79,23 +94,23 @@ nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng, case NV_MEM_ACCESS_VM: break; case NV_MEM_ACCESS_RO: - flags |= 0x00040000; + flags0 |= 0x00040000; break; case NV_MEM_ACCESS_WO: case NV_MEM_ACCESS_RW: - flags |= 0x00080000; + flags0 |= 0x00080000; break; } ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { - nv_wo32(*pgpuobj, 0x00, flags); + nv_wo32(*pgpuobj, 0x00, flags0); nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit)); nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start)); nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 | upper_32_bits(dmaobj->start)); nv_wo32(*pgpuobj, 0x10, 0x00000000); - nv_wo32(*pgpuobj, 0x14, 0x00000000); + nv_wo32(*pgpuobj, 0x14, flags5); } return ret; |