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| author | Archit Taneja <architt@codeaurora.org> | 2017-03-23 15:58:04 +0530 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2017-04-08 06:59:34 -0400 |
| commit | bcb877b7fdeaf0867d3363136644e4d378207e31 (patch) | |
| tree | dcdf8453931fd58758c6b9374f565a944ca0f256 /drivers/gpu/drm/msm | |
| parent | 502e3550c6f58f514d57f9e13ec9a98f6936b243 (diff) | |
| download | op-kernel-dev-bcb877b7fdeaf0867d3363136644e4d378207e31.zip op-kernel-dev-bcb877b7fdeaf0867d3363136644e4d378207e31.tar.gz | |
drm/msm/mdp5: Add more stuff to CRTC state
Things like vblank/err irq masks, mode of operation (command mode or not)
are derivative of the interface and mixer state. Therefore, they need to
be a part of the CRTC state too.
Add them to mdp5_crtc_state, and assign them in the CRTC's atomic_check()
func, so that it can be rolled back to a clean state.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm')
| -rw-r--r-- | drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 19 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 7 |
2 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 9cfad3d..7913e93 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -373,6 +373,7 @@ int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(new_crtc_state); struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; + struct mdp5_interface *intf; bool new_mixer = false; new_mixer = !pipeline->mixer; @@ -388,6 +389,24 @@ int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, mdp5_mixer_release(new_crtc_state->state, old_mixer); } + /* + * these should have been already set up in the encoder's atomic + * check (called by drm_atomic_helper_check_modeset) + */ + intf = pipeline->intf; + + mdp5_cstate->err_irqmask = intf2err(intf->num); + mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); + + if ((intf->type == INTF_DSI) && + (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { + mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); + mdp5_cstate->cmd_mode = true; + } else { + mdp5_cstate->pp_done_irqmask = 0; + mdp5_cstate->cmd_mode = false; + } + return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 35f3c30..35a21e6 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -126,6 +126,13 @@ struct mdp5_crtc_state { struct mdp5_ctl *ctl; struct mdp5_pipeline pipeline; + + /* these are derivatives of intf/mixer state in mdp5_pipeline */ + u32 vblank_irqmask; + u32 err_irqmask; + u32 pp_done_irqmask; + + bool cmd_mode; }; #define to_mdp5_crtc_state(x) \ container_of(x, struct mdp5_crtc_state, base) |
