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authorArchit Taneja <architt@codeaurora.org>2016-05-07 23:11:25 +0530
committerRob Clark <robdclark@gmail.com>2016-07-16 10:08:51 -0400
commit990a40079a55b81b5b6aef91a24aa053fb370072 (patch)
treee5dd69f557661d99cb4f48ac6cfee7f9cc513428 /drivers/gpu/drm/msm/msm_drv.c
parenta2b3a5571f386e23b56164396292675bac6f2a19 (diff)
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op-kernel-dev-990a40079a55b81b5b6aef91a24aa053fb370072.tar.gz
drm/msm/mdp5: Add MDSS top level driver
SoCs that contain MDP5 have a top level wrapper called MDSS that manages clocks, power and irq for the sub-blocks within it. Currently, the MDSS portions are stuffed into the MDP5 driver. This makes it hard to represent the DT bindings in the correct way. We create a top level MDSS helper that handles these parts. This is essentially moving out some of the mdp5_kms irq code and MDSS register space and keeping it as a separate entity. We haven't given any clocks to the top level MDSS yet, but a AHB clock would be added in the future to access registers. One thing to note is that the resources allocated by this helper are tied to the top level platform_device (the one that allocates the drm_device struct too). This device would be the parent to MDSS sub-blocks like MDP5, DSI, eDP etc. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/msm_drv.c')
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