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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-04-28 14:29:45 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-05-13 17:08:31 -0700 |
| commit | fe100d4da1ba8e0be9f38979da1817145e68f866 (patch) | |
| tree | 913bfd6954a0a7a16213bd2f271127b668046758 /drivers/gpu/drm/i915 | |
| parent | 357555c00f8414057f0c12ee3f479f197264123d (diff) | |
| download | op-kernel-dev-fe100d4da1ba8e0be9f38979da1817145e68f866.zip op-kernel-dev-fe100d4da1ba8e0be9f38979da1817145e68f866.tar.gz | |
drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
Not fully tested.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5ccd18f..b1de6cb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7298,7 +7298,7 @@ void intel_enable_clock_gating(struct drm_device *dev) _3D_CHICKEN2_WM_READ_PIPELINED); } - if (IS_GEN6(dev)) { + if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { I915_WRITE(WM3_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); @@ -7560,6 +7560,13 @@ static void intel_init_display(struct drm_device *dev) } else if (IS_IVYBRIDGE(dev)) { /* FIXME: detect B0+ stepping and use auto training */ dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; + if (SNB_READ_WM0_LATENCY()) { + dev_priv->display.update_wm = sandybridge_update_wm; + } else { + DRM_DEBUG_KMS("Failed to read display plane latency. " + "Disable CxSR\n"); + dev_priv->display.update_wm = NULL; + } } else dev_priv->display.update_wm = NULL; } else if (IS_PINEVIEW(dev)) { |
