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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2014-12-16 08:44:32 +0000 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2014-12-16 15:06:48 +0200 |
| commit | add284a3a2481e759d6bec35f6444c32c8ddc383 (patch) | |
| tree | 0025131e13d320a2a644f375a869f93a41311873 /drivers/gpu/drm/i915 | |
| parent | 148b83d0815a3778c8949e6a97cb798cbaa0efb3 (diff) | |
| download | op-kernel-dev-add284a3a2481e759d6bec35f6444c32c8ddc383.zip op-kernel-dev-add284a3a2481e759d6bec35f6444c32c8ddc383.tar.gz | |
drm/i915: Force the CS stall for invalidate flushes
In order to act as a full command barrier by itself, we need to tell the
pipecontrol to actually stall the command streamer while the flush runs.
We require the full command barrier before operations like
MI_SET_CONTEXT, which currently rely on a prior invalidate flush.
References: https://bugs.freedesktop.org/show_bug.cgi?id=83677
Cc: Simon Farnsworth <simon@farnz.org.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3d6bc8d..c7bc93d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -369,6 +369,8 @@ gen7_render_ring_flush(struct intel_engine_cs *ring, flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; + /* Workaround: we must issue a pipe_control with CS-stall bit * set before a pipe_control command that has the state cache * invalidate bit set. */ |
