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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-01-12 21:08:36 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-01-13 18:46:44 +0200 |
| commit | ce1e5c140ce945ef6fc4ee4803f0c2f774873d8f (patch) | |
| tree | 4e1dca90cc894e651e9f883bb2510558402aec11 /drivers/gpu/drm/i915/intel_sprite.c | |
| parent | d843310d146452105e2bc54b8d82e52ad727697f (diff) | |
| download | op-kernel-dev-ce1e5c140ce945ef6fc4ee4803f0c2f774873d8f.zip op-kernel-dev-ce1e5c140ce945ef6fc4ee4803f0c2f774873d8f.tar.gz | |
drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/
Since intel_gen4_compute_page_offset() can now handle tiling formats
all the way down to gen2, rename it to intel_compute_tile_offset().
Not that we actually use it on gen2/3 since there's no DSPSURF etc.
registers which would take a page aligned address.
v2: s/page/tile/ (Daniel)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1452625717-9713-7-git-send-email-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sprite.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_sprite.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 64083d7..22589fc 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -423,10 +423,10 @@ vlv_update_plane(struct drm_plane *dplane, crtc_h--; linear_offset = y * fb->pitches[0] + x * pixel_size; - sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y, - fb->modifier[0], - pixel_size, - fb->pitches[0]); + sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y, + fb->modifier[0], + pixel_size, + fb->pitches[0]); linear_offset -= sprsurf_offset; if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { @@ -557,10 +557,10 @@ ivb_update_plane(struct drm_plane *plane, sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; linear_offset = y * fb->pitches[0] + x * pixel_size; - sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y, - fb->modifier[0], - pixel_size, - fb->pitches[0]); + sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y, + fb->modifier[0], + pixel_size, + fb->pitches[0]); linear_offset -= sprsurf_offset; if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { @@ -696,10 +696,10 @@ ilk_update_plane(struct drm_plane *plane, dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; linear_offset = y * fb->pitches[0] + x * pixel_size; - dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y, - fb->modifier[0], - pixel_size, - fb->pitches[0]); + dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y, + fb->modifier[0], + pixel_size, + fb->pitches[0]); linear_offset -= dvssurf_offset; if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
