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authorImre Deak <imre.deak@intel.com>2015-11-04 19:24:19 +0200
committerImre Deak <imre.deak@intel.com>2015-11-17 20:55:16 +0200
commitc2b16152e0b3112fb5a45da243b85f8a737fd2ee (patch)
treeb6c5e3c5b5d8957fbb67a01bf22c7f3eebe17c4b /drivers/gpu/drm/i915/intel_runtime_pm.c
parentab96c1ee1757a7a96dc2fd4e466747633e43cb0d (diff)
downloadop-kernel-dev-c2b16152e0b3112fb5a45da243b85f8a737fd2ee.zip
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drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enabling
We don't need to reinit DDI and IRQs during PW1 enabling any more, since we don't toggle PW1 on-demand any more. We enable PW1 only as part of the display core init sequence and after this we initialize both DDI and IRQs later in the init sequence. So remove these init steps from the power well code. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446657859-9598-11-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4b3ae49..238ba74 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -244,11 +244,6 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
gen8_irq_power_well_post_enable(dev_priv,
1 << PIPE_C | 1 << PIPE_B);
}
-
- if (power_well->data == SKL_DISP_PW_1) {
- intel_prepare_ddi(dev);
- gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
- }
}
static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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