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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2017-08-21 17:03:56 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-22 09:22:45 -0700 |
| commit | ade5ee7ea55daab37a300374c73aceb3092ccdd6 (patch) | |
| tree | 6e555994fddc023ddd6f0ab8066c9e4c5dd83cd9 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | e0b8acf35d3c4de3d9b4bde18169e0562d748c89 (diff) | |
| download | op-kernel-dev-ade5ee7ea55daab37a300374c73aceb3092ccdd6.zip op-kernel-dev-ade5ee7ea55daab37a300374c73aceb3092ccdd6.tar.gz | |
drm/i915/cnl: extract cnl_set_procmon_ref_values
Move the part that reads the table and sets registers based on the
table to its own function.
v2: Rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170822000356.17330-2-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index b7f4fbe..a3bfb9f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2730,25 +2730,11 @@ static const struct cnl_procmon { { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, }; -static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) +static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv) { - struct i915_power_domains *power_domains = &dev_priv->power_domains; const struct cnl_procmon *procmon; - struct i915_power_well *well; u32 val; - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - - /* 1. Enable PCH Reset Handshake */ - val = I915_READ(HSW_NDE_RSTWRN_OPT); - val |= RESET_PCH_HANDSHAKE_ENABLE; - I915_WRITE(HSW_NDE_RSTWRN_OPT, val); - - /* 2. Enable Comp */ - val = I915_READ(CHICKEN_MISC_2); - val &= ~CNL_COMP_PWR_DOWN; - I915_WRITE(CHICKEN_MISC_2, val); - val = I915_READ(CNL_PORT_COMP_DW3); switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { default: @@ -2777,6 +2763,27 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9); I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10); +} + +static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) +{ + struct i915_power_domains *power_domains = &dev_priv->power_domains; + struct i915_power_well *well; + u32 val; + + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + + /* 1. Enable PCH Reset Handshake */ + val = I915_READ(HSW_NDE_RSTWRN_OPT); + val |= RESET_PCH_HANDSHAKE_ENABLE; + I915_WRITE(HSW_NDE_RSTWRN_OPT, val); + + /* 2. Enable Comp */ + val = I915_READ(CHICKEN_MISC_2); + val &= ~CNL_COMP_PWR_DOWN; + I915_WRITE(CHICKEN_MISC_2, val); + + cnl_set_procmon_ref_values(dev_priv); val = I915_READ(CNL_PORT_COMP_DW0); val |= COMP_INIT; |
