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| author | Damien Lespiau <damien.lespiau@intel.com> | 2014-03-13 01:40:28 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-13 03:52:31 +0100 |
| commit | dc616b89dbc4bb6a99884d214bd1ed1e0eef59a0 (patch) | |
| tree | 18a0547a3e6b620cb308b58ca7137f436baca1b8 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | 065f2ec2afc850960dcebc3b00766bc31c4ffd3b (diff) | |
| download | op-kernel-dev-dc616b89dbc4bb6a99884d214bd1ed1e0eef59a0.zip op-kernel-dev-dc616b89dbc4bb6a99884d214bd1ed1e0eef59a0.tar.gz | |
drm/i915/bdw: The TLB invalidation mechanism has been removed from INSTPM
While wandering in the spec, I noticed that BDW removes those 2 bits
from INSTPM. I couldn't find any direct way to invalidate the TLB (ie
without the ring working already). Maybe someone will be more lucky.
At least, we now know we may be a problem.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index c50388a..4eb3e06 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -981,8 +981,14 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); POSTING_READ(mmio); - /* Flush the TLB for this page */ - if (INTEL_INFO(dev)->gen >= 6) { + /* + * Flush the TLB for this page + * + * FIXME: These two bits have disappeared on gen8, so a question + * arises: do we still need this and if so how should we go about + * invalidating the TLB? + */ + if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { u32 reg = RING_INSTPM(ring->mmio_base); /* ring should be idle before issuing a sync flush*/ |
