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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2014-03-21 17:18:54 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-04-01 22:58:04 +0200 |
| commit | aa83e30d8f71c966498f8f7f587514283c47e1b6 (patch) | |
| tree | 5b28f076a1a09253ed597a872e4a983e18bf7cbc /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | c8431fda9f9f3c3b7490cb44bd5720b494a2421e (diff) | |
| download | op-kernel-dev-aa83e30d8f71c966498f8f7f587514283c47e1b6.zip op-kernel-dev-aa83e30d8f71c966498f8f7f587514283c47e1b6.tar.gz | |
drm/i915: Rename GFX_TLB_INVALIDATE_ALWAYS
The documentation calls this GFX_MODE bit "Flush TLB invalidate Mode".
However, that is not a good name for an enable bit as it doesn't make it
clear what is enabled. An even worse name is GFX_TLB_INVALIDATE_ALWAYS
as enabling that bit actually prevents the TLB from being invalidated at
every flush. This leads to great confusion when reading code and
proposed patches. To get around this try to bake in what is enabled by
setting the bit and call it GFX_TLB_INVALIDATE_EXPLICIT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Gupta, Sourab" <sourab.gupta@intel.com>
Acked-by: "Gupta, Sourab" <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 6bc68bd..64a0ecf 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -589,11 +589,11 @@ static int init_render_ring(struct intel_ring_buffer *ring) /* Required for the hardware to program scanline values for waiting */ if (INTEL_INFO(dev)->gen == 6) I915_WRITE(GFX_MODE, - _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); if (IS_GEN7(dev)) I915_WRITE(GFX_MODE_GEN7, - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_EXPLICIT) | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); if (INTEL_INFO(dev)->gen >= 5) { @@ -616,7 +616,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) * TODO: consider explicitly setting the bit for GEN5 */ ring->itlb_before_ctx_switch = - !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); + !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_EXPLICIT); } if (INTEL_INFO(dev)->gen >= 6) |
