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| author | Tom O'Rourke <Tom.O'Rourke@intel.com> | 2014-04-09 11:44:06 -0700 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2014-07-02 13:31:10 +0300 |
| commit | 0d68b25e9ceb344fe2f93373b1c0311d33814265 (patch) | |
| tree | 3db8b6c770270035b3b6dd90e57c8e64b41f1036 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 84a2ab8ec76b4fa47f490a01c8186e4b4d757bfe (diff) | |
| download | op-kernel-dev-0d68b25e9ceb344fe2f93373b1c0311d33814265.zip op-kernel-dev-0d68b25e9ceb344fe2f93373b1c0311d33814265.tar.gz | |
drm/i915/bdw: Use timeout mode for RC6 on bdw
Higher RC6 residency is observed using timeout mode
instead of EI mode. This applies to Broadwell only.
The difference is particularly noticeable with video
playback.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1cce0a5..cb26145 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3486,15 +3486,23 @@ static void gen8_enable_rps(struct drm_device *dev) for_each_ring(ring, dev_priv, unused) I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); I915_WRITE(GEN6_RC_SLEEP, 0); - I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ + if (IS_BROADWELL(dev)) + I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ + else + I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ /* 3: Enable RC6 */ if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) rc6_mask = GEN6_RC_CTL_RC6_ENABLE; intel_print_rc6_info(dev, rc6_mask); - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | - GEN6_RC_CTL_EI_MODE(1) | - rc6_mask); + if (IS_BROADWELL(dev)) + I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | + GEN7_RC_CTL_TO_MODE | + rc6_mask); + else + I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | + GEN6_RC_CTL_EI_MODE(1) | + rc6_mask); /* 4 Program defaults and thresholds for RPS*/ I915_WRITE(GEN6_RPNSWREQ, |
