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| author | Ben Widawsky <ben@bwidawsk.net> | 2013-11-02 21:07:59 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-08 18:10:06 +0100 |
| commit | a75f36283d12d13aa278abce3a1bb6662e28fcfb (patch) | |
| tree | 3f286a9ab97ad12b99143c5a936f1c5188121660 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 7f88da0cf6947c3b6a5ccad6c37336367dd69159 (diff) | |
| download | op-kernel-dev-a75f36283d12d13aa278abce3a1bb6662e28fcfb.zip op-kernel-dev-a75f36283d12d13aa278abce3a1bb6662e28fcfb.tar.gz | |
drm/i915/bdw: conservative SBE VUE cache mode
Hold vertex data in cache until last reference
BDW-A workaround
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5dceb56..ccd1b88 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5297,6 +5297,9 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(_3D_CHICKEN3, _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); + I915_WRITE(COMMON_SLICE_CHICKEN2, + _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); + /* WaSwitchSolVfFArbitrationPriority */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
