diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-04-21 21:14:28 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-05-10 16:48:31 +0300 |
| commit | 42f4ac66c5352d3b84aa5119b3419750ec57e008 (patch) | |
| tree | 2eef4ccb39fe7243810b17e9fd1832b2afb67842 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | baf69ca8a51c8a5ef6ef869f684764459a9b6fa2 (diff) | |
| download | op-kernel-dev-42f4ac66c5352d3b84aa5119b3419750ec57e008.zip op-kernel-dev-42f4ac66c5352d3b84aa5119b3419750ec57e008.tar.gz | |
drm/i915: Apply the g4x TLB miss w/a to SR watermarks as well
The documentation I've seen doesn't actually specify which watermarks
need the TLB miss w/a. Currently we only apply the w/a to the normal
watermarks for both primary and cursor planes. Since the documentation
doesn't explicitly say anything I'm going to assume that the w/a should
equally apply to the SR/HPLL watermarks. So let's do that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170421181432.15216-12-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c07f3b2..61b6799 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1006,7 +1006,7 @@ static bool g4x_compute_srwm(struct drm_i915_private *dev_priv, struct intel_crtc *crtc; const struct drm_display_mode *adjusted_mode; const struct drm_framebuffer *fb; - int hdisplay, htotal, cpp, clock; + int plane_width, cursor_width, htotal, cpp, clock; int small, large; int entries; @@ -1020,20 +1020,23 @@ static bool g4x_compute_srwm(struct drm_i915_private *dev_priv, fb = crtc->base.primary->state->fb; clock = adjusted_mode->crtc_clock; htotal = adjusted_mode->crtc_htotal; - hdisplay = crtc->config->pipe_src_w; + plane_width = crtc->config->pipe_src_w; + cursor_width = crtc->base.cursor->state->crtc_w; cpp = fb->format->cpp[0]; /* Use the minimum of the small and large buffer method for primary */ small = intel_wm_method1(clock, cpp, latency_ns / 100); - large = intel_wm_method2(clock, htotal, hdisplay, cpp, + large = intel_wm_method2(clock, htotal, plane_width, cpp, latency_ns / 100); - entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); + entries = min(small, large); + entries += g4x_tlb_miss_wa(display->fifo_size, plane_width, cpp); + entries = DIV_ROUND_UP(entries, display->cacheline_size); *display_wm = entries + display->guard_size; /* calculate the self-refresh watermark for display cursor */ - entries = intel_wm_method2(clock, htotal, - crtc->base.cursor->state->crtc_w, 4, + entries = intel_wm_method2(clock, htotal, cursor_width, 4, latency_ns / 100); + entries += g4x_tlb_miss_wa(cursor->fifo_size, cursor_width, 4); entries = DIV_ROUND_UP(entries, cursor->cacheline_size); *cursor_wm = entries + cursor->guard_size; |
