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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-11-04 23:20:10 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-11-18 14:35:36 +0200 |
| commit | 35dc3f97a69bb344768c6a2f47da2be46b11645a (patch) | |
| tree | 0ef4a4a9adc9f7d6c8cb2d9cb787188a50744b7e /drivers/gpu/drm/i915/intel_lrc.c | |
| parent | 9244a817019f25602a2bad230892c42983da51e7 (diff) | |
| download | op-kernel-dev-35dc3f97a69bb344768c6a2f47da2be46b11645a.zip op-kernel-dev-35dc3f97a69bb344768c6a2f47da2be46b11645a.tar.gz | |
drm/i915: Give names to more ring registers
The logical render context population has a bunch of raw ring register
offsets. Use the names we have for them, and in cases where we we don't,
give them names.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-23-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index b641c5a..ebbd64e 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2261,24 +2261,24 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); reg_state[CTX_RING_BUFFER_CONTROL+1] = ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; - reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; + reg_state[CTX_BB_HEAD_U] = RING_BBADDR_UDW(ring->mmio_base); reg_state[CTX_BB_HEAD_U+1] = 0; - reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; + reg_state[CTX_BB_HEAD_L] = RING_BBADDR(ring->mmio_base); reg_state[CTX_BB_HEAD_L+1] = 0; - reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; - reg_state[CTX_BB_STATE+1] = (1<<5); - reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; + reg_state[CTX_BB_STATE] = RING_BBSTATE(ring->mmio_base); + reg_state[CTX_BB_STATE+1] = RING_BB_PPGTT; + reg_state[CTX_SECOND_BB_HEAD_U] = RING_SBBADDR_UDW(ring->mmio_base); reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; - reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; + reg_state[CTX_SECOND_BB_HEAD_L] = RING_SBBADDR(ring->mmio_base); reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; - reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; + reg_state[CTX_SECOND_BB_STATE] = RING_SBBSTATE(ring->mmio_base); reg_state[CTX_SECOND_BB_STATE+1] = 0; if (ring->id == RCS) { - reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; + reg_state[CTX_BB_PER_CTX_PTR] = RING_BB_PER_CTX_PTR(ring->mmio_base); reg_state[CTX_BB_PER_CTX_PTR+1] = 0; - reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; + reg_state[CTX_RCS_INDIRECT_CTX] = RING_INDIRECT_CTX(ring->mmio_base); reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; - reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; + reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = RING_INDIRECT_CTX_OFFSET(ring->mmio_base); reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; if (ring->wa_ctx.obj) { struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; @@ -2298,7 +2298,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o } reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; - reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; + reg_state[CTX_CTX_TIMESTAMP] = RING_CTX_TIMESTAMP(ring->mmio_base); reg_state[CTX_CTX_TIMESTAMP+1] = 0; reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); |
