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authorTvrtko Ursulin <tvrtko.ursulin@intel.com>2016-01-15 15:10:28 +0000
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2016-01-18 09:58:40 +0000
commit0eb973d31d0aadb6bc801fd6d796afecbbfc3d5b (patch)
tree19a254daa12645b56c2d5cacf9d6c17409564803 /drivers/gpu/drm/i915/intel_lrc.c
parentca82580c9ceace0d52fe7376b8a72bb3b36f612b (diff)
downloadop-kernel-dev-0eb973d31d0aadb6bc801fd6d796afecbbfc3d5b.zip
op-kernel-dev-0eb973d31d0aadb6bc801fd6d796afecbbfc3d5b.tar.gz
drm/i915: Cache ringbuffer GTT VMA
Purpose is to avoid calling i915_gem_obj_ggtt_offset from the interrupt context without the big lock held. v2: Renamed gtt_start to gtt_offset. (Daniel Vetter) v3: Cache the VMA instead of address. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1452870629-13830-2-git-send-email-tvrtko.ursulin@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.c')
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 86042dc..588cad58 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -391,7 +391,6 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
struct intel_engine_cs *ring = rq->ring;
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
- struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
struct page *page;
uint32_t *reg_state;
@@ -401,7 +400,7 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
reg_state = kmap_atomic(page);
reg_state[CTX_RING_TAIL+1] = rq->tail;
- reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
+ reg_state[CTX_RING_BUFFER_START+1] = rq->ringbuf->vma->node.start;
if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
/* True 32b PPGTT with dynamic page allocation: update PDP
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