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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-02-01 09:01:13 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-02-01 09:01:13 +0000 |
| commit | 8f9a3f9b63b8cd3f03be9dc53533f90bd4120e5f (patch) | |
| tree | ed2c674e8b4738a9b1c87785cef40b4e427ab526 /drivers/gpu/drm/i915/intel_i2c.c | |
| parent | 4a1dc3ff68807bf3c76563bf439166854d063adc (diff) | |
| download | op-kernel-dev-8f9a3f9b63b8cd3f03be9dc53533f90bd4120e5f.zip op-kernel-dev-8f9a3f9b63b8cd3f03be9dc53533f90bd4120e5f.tar.gz | |
drm/i915: Enable GMBUS for post-gen2 chipsets
With the recent SDVO fix, this is working on all the machines I have to
hand - except for an 845G.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_i2c.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_i2c.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 58040f6..82d04c5 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -384,7 +384,8 @@ int intel_setup_gmbus(struct drm_device *dev) bus->reg0 = i | GMBUS_RATE_100KHZ; /* XXX force bit banging until GMBUS is fully debugged */ - bus->force_bit = intel_gpio_create(dev_priv, i); + if (IS_GEN2(dev)) + bus->force_bit = intel_gpio_create(dev_priv, i); } intel_i2c_reset(dev_priv->dev); |
