diff options
| author | daniele.ceraolospurio@intel.com <daniele.ceraolospurio@intel.com> | 2017-04-06 17:18:52 -0700 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2017-04-13 14:01:01 +0300 |
| commit | 13f6c719eb88f2a0c8981d7a0c45404194aa2ef5 (patch) | |
| tree | f8f59efe490e40e7820b2318e2990ee705c572f2 /drivers/gpu/drm/i915/intel_guc_loader.c | |
| parent | 48ae80741da4b8a26b6df0f765713912bc7cc480 (diff) | |
| download | op-kernel-dev-13f6c719eb88f2a0c8981d7a0c45404194aa2ef5.zip op-kernel-dev-13f6c719eb88f2a0c8981d7a0c45404194aa2ef5.tar.gz | |
drm/i915/guc: write wopcm related register once during uc init
The wopcm registers are write-once, so any write after the first one
will just be ignored. The registers survive a GPU reset but not
always a suspend/resume cycle, so to keep things simple keep the
writes in the intel_uc_init_hw function instead of moving it earlier
to make sure we attempt them every time we try to load GuC.
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1491524332-23860-1-git-send-email-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_loader.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc_loader.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 12f80ec..d9045b6 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -285,10 +285,6 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - /* init WOPCM */ - I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv)); - I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); - /* Enable MIA caching. GuC clock gating is disabled. */ I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); |
