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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2016-08-24 19:00:53 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-08-24 19:32:35 +0100 |
| commit | c82dd8848479d27dec3f05e9a0980a83fcadca8b (patch) | |
| tree | d5a389b774eb4af4b0ed603ef3bb3fd95deedb12 /drivers/gpu/drm/i915/intel_fbc.c | |
| parent | 38cb2ecaf56fac390bd337f5f8140dc4bc34c27e (diff) | |
| download | op-kernel-dev-c82dd8848479d27dec3f05e9a0980a83fcadca8b.zip op-kernel-dev-c82dd8848479d27dec3f05e9a0980a83fcadca8b.tar.gz | |
Revert "drm/i915/fbc: Allow on unfenced surfaces, for recent gen"
This reverts commit 8678fdaf396c ("drm/i915/fbc: Allow on unfenced surfaces,
for recent gen") as Skylake has issues with unfenced FBC tracking (and
yes Skylake doesn't even enable FBC yet). Paulo would like to do a full
review of all existing workarounds to see if any more are missing prior
to allowing FBC on unfenced surfaces. In the meantime lets hope that all
framebuffers are idle and naturally fit within the mappable aperture.
Requested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Fixes: 8678fdaf396c ("drm/i915/fbc: Allow on unfenced surfaces...");
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160824180053.24239-1-chris@chris-wilson.co.uk
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_fbc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_fbc.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index bf8b22a..faa6762 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -799,10 +799,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) */ if (cache->fb.tiling_mode != I915_TILING_X || cache->fb.fence_reg == I915_FENCE_REG_NONE) { - if (INTEL_GEN(dev_priv) < 5) { - fbc->no_fbc_reason = "framebuffer not tiled or fenced"; - return false; - } + fbc->no_fbc_reason = "framebuffer not tiled or fenced"; + return false; } if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && cache->plane.rotation != DRM_ROTATE_0) { |
