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author | Jani Nikula <jani.nikula@intel.com> | 2013-08-27 15:12:19 +0300 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-09-04 17:34:47 +0200 |
commit | 69c05eb2d8421cbe96c2c66ea6e3223d25928d92 (patch) | |
tree | 7c09818adfde64ecbd81d5f562914b1f82de64eb /drivers/gpu/drm/i915/intel_dsi_cmd.h | |
parent | f5e11b06eb8a5aa6d4918aca85f88268e131a88e (diff) | |
download | op-kernel-dev-69c05eb2d8421cbe96c2c66ea6e3223d25928d92.zip op-kernel-dev-69c05eb2d8421cbe96c2c66ea6e3223d25928d92.tar.gz |
drm/i915: add MIPI DSI command sending routines
v2: Rebase due to register bit definition change.
v3: Mostly based on Ville's review comments.
- Use size_t for length all around.
- Reuse dsi_vc_send_short in dsi_vc_send_long.
- Remove stale/incorrect comments.
- Reverse special packet sent interrupt check.
- Use DSI controller regs for reading, not adapter.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi_cmd.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h new file mode 100644 index 0000000..714a49a --- /dev/null +++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h @@ -0,0 +1,109 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Jani Nikula <jani.nikula@intel.com> + */ + +#ifndef _INTEL_DSI_DSI_H +#define _INTEL_DSI_DSI_H + +#include <drm/drmP.h> +#include <drm/drm_crtc.h> +#include <video/mipi_display.h> +#include "i915_drv.h" +#include "intel_drv.h" +#include "intel_dsi.h" + +void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable); + +int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel, + const u8 *data, size_t len); + +int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel, + const u8 *data, size_t len); + +int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd, + u8 *buf, size_t buflen); + +int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel, + u8 *reqdata, size_t reqlen, u8 *buf, size_t buflen); + +int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd); + +/* XXX: questionable write helpers */ +static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi, + int channel, u8 dcs_cmd) +{ + return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1); +} + +static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi, + int channel, u8 dcs_cmd, u8 param) +{ + u8 buf[2] = { dcs_cmd, param }; + return dsi_vc_dcs_write(intel_dsi, channel, buf, 2); +} + +static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi, + int channel) +{ + return dsi_vc_generic_write(intel_dsi, channel, NULL, 0); +} + +static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi, + int channel, u8 param) +{ + return dsi_vc_generic_write(intel_dsi, channel, ¶m, 1); +} + +static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi, + int channel, u8 param1, u8 param2) +{ + u8 buf[2] = { param1, param2 }; + return dsi_vc_generic_write(intel_dsi, channel, buf, 2); +} + +/* XXX: questionable read helpers */ +static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi, + int channel, u8 *buf, size_t buflen) +{ + return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen); +} + +static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi, + int channel, u8 param, u8 *buf, + size_t buflen) +{ + return dsi_vc_generic_read(intel_dsi, channel, ¶m, 1, buf, buflen); +} + +static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi, + int channel, u8 param1, u8 param2, + u8 *buf, size_t buflen) +{ + u8 req[2] = { param1, param2 }; + + return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen); +} + + +#endif /* _INTEL_DSI_DSI_H */ |