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| author | Shashank Sharma <shashank.sharma@intel.com> | 2015-09-01 19:41:46 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-10-02 14:45:51 +0200 |
| commit | ce0c982152137789e6f09e9d8712034088adf3aa (patch) | |
| tree | 084e10b2769d97dd488696742b11a1b6c8fc5ab0 /drivers/gpu/drm/i915/intel_dsi.c | |
| parent | baeac68a82f07f7c37bfc3d9624127b813a8d8b4 (diff) | |
| download | op-kernel-dev-ce0c982152137789e6f09e9d8712034088adf3aa.zip op-kernel-dev-ce0c982152137789e6f09e9d8712034088adf3aa.tar.gz | |
drm/i915/bxt: get DSI pixelclock
BXT's DSI PLL is different from that of VLV. So this patch
adds a new function to get the current DSI pixel clock based
on the PLL divider ratio and lane count.
This function is required for intel_dsi_get_config() function.
v2: Fixed Jani's review comments.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dsi.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 6591106..170ae6f 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -695,7 +695,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, static void intel_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - u32 pclk; + u32 pclk = 0; DRM_DEBUG_KMS("\n"); /* @@ -704,7 +704,11 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, */ pipe_config->dpll_hw_state.dpll_md = 0; - pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + if (IS_BROXTON(encoder->base.dev)) + pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + else if (IS_VALLEYVIEW(encoder->base.dev)) + pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + if (!pclk) return; |
