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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-11-24 18:28:11 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-03 09:29:38 +0100 |
| commit | 7514747d27632f2d71dd2f1e6abd6e0451dcbf3f (patch) | |
| tree | a8af68e60bd807b19b7e090fa26743ce3e0092a7 /drivers/gpu/drm/i915/intel_drv.h | |
| parent | 408d4b9e1f0159583e81e093b3e7fe12a9b1072f (diff) | |
| download | op-kernel-dev-7514747d27632f2d71dd2f1e6abd6e0451dcbf3f.zip op-kernel-dev-7514747d27632f2d71dd2f1e6abd6e0451dcbf3f.tar.gz | |
drm/i915: Grab modeset locks for GPU rest on pre-ctg
On gen4 and earlier the GPU reset also resets the display, so we should
protect against concurrent modeset operations. Grab all the modeset locks
around the entire GPU reset dance, remebering first ti dislogde any
pending page flip to make sure we don't deadlock. Any pageflip coming
in between these two steps should fail anyway due to reset_in_progress,
so this should be safe.
This fixes a lot of failed asserts in the modeset code when there's a
modeset racing with the reset. Naturally the asserts aren't happy when
the expected state has disappeared.
v2: Drop UMS checks, complete pending flips after the reset (Daniel)
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f0a46ec..25fdbb1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -958,7 +958,8 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y, unsigned int tiling_mode, unsigned int bpp, unsigned int pitch); -void intel_display_handle_reset(struct drm_device *dev); +void intel_prepare_reset(struct drm_device *dev); +void intel_finish_reset(struct drm_device *dev); void hsw_enable_pc8(struct drm_i915_private *dev_priv); void hsw_disable_pc8(struct drm_i915_private *dev_priv); void intel_dp_get_m_n(struct intel_crtc *crtc, |
