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authorMatt Roper <matthew.d.roper@intel.com>2016-01-19 11:43:04 -0800
committerDaniel Vetter <daniel.vetter@ffwll.ch>2016-01-20 10:07:22 +0100
commitbf22045250fafbe733277e13300eaa240ba2104d (patch)
tree4ac126dac777ed525cd36096bfd78c6cce78750c /drivers/gpu/drm/i915/intel_drv.h
parent18afd443f7f92c3cf514af531e020c8d992e49ac (diff)
downloadop-kernel-dev-bf22045250fafbe733277e13300eaa240ba2104d.zip
op-kernel-dev-bf22045250fafbe733277e13300eaa240ba2104d.tar.gz
Revert "drm/i915: Add two-stage ILK-style watermark programming (v10)"
This reverts commit 396e33ae204f52abebec9e578f44c749305500f4. This commit was triggering some FIFO underrun warnings on ILK-IVB platforms (but surprisingly not on HSW/BDW that share more or less the same codepaths). These underruns were caught by the continuous integration (CI) system and could be reproduced consistently when running the basic acceptance tests (BAT) on the affected platforms. Note that this revert will cause a visible regression for some end-users; the "flicker when mouse moves between monitors in X" issue that was reported before this patch was merged will now return. However regressions that are visible to CI have higher priority since they prevent proper testing of future patches on those platforms. Hopefully we'll be able to figure out the cause of the underruns quickly and remerge an improved version of this patch to fix the regression. Cc: Daniel Vetter <daniel@ffwll.ch> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93640 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Daniel Vetter <daniel@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1453232584-8543-1-git-send-email-matthew.d.roper@intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h28
1 files changed, 2 insertions, 26 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 059b46e..15917e3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -260,12 +260,6 @@ struct intel_atomic_state {
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
struct intel_wm_config wm_config;
-
- /*
- * Current watermarks can't be trusted during hardware readout, so
- * don't bother calculating intermediate watermarks.
- */
- bool skip_intermediate_wm;
};
struct intel_plane_state {
@@ -513,29 +507,13 @@ struct intel_crtc_state {
struct {
/*
- * Optimal watermarks, programmed post-vblank when this state
- * is committed.
+ * optimal watermarks, programmed post-vblank when this state
+ * is committed
*/
union {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
} optimal;
-
- /*
- * Intermediate watermarks; these can be programmed immediately
- * since they satisfy both the current configuration we're
- * switching away from and the new configuration we're switching
- * to.
- */
- struct intel_pipe_wm intermediate;
-
- /*
- * Platforms with two-step watermark programming will need to
- * update watermark programming post-vblank to switch from the
- * safe intermediate watermarks to the optimal final
- * watermarks.
- */
- bool need_postvbl_update;
} wm;
};
@@ -622,7 +600,6 @@ struct intel_crtc {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
} active;
-
/* allow CxSR on this pipe */
bool cxsr_allowed;
} wm;
@@ -1583,7 +1560,6 @@ void skl_wm_get_hw_state(struct drm_device *dev);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb /* out */);
uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
-bool ilk_disable_lp_wm(struct drm_device *dev);
/* intel_sdvo.c */
bool intel_sdvo_init(struct drm_device *dev,
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