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authorYetunde Adebisi <yetundex.adebisi@intel.com>2016-04-05 15:10:51 +0100
committerJani Nikula <jani.nikula@intel.com>2016-04-26 15:04:06 +0300
commit86ee27b5aa7591506e4a706881ea8aaec02ccb50 (patch)
tree7872ffa4b160733207dc804b0edf85fb3fa3f92f /drivers/gpu/drm/i915/intel_drv.h
parent4e382db36cf50969f6bafb1ac99ae6c3f5bf5568 (diff)
downloadop-kernel-dev-86ee27b5aa7591506e4a706881ea8aaec02ccb50.zip
op-kernel-dev-86ee27b5aa7591506e4a706881ea8aaec02ccb50.tar.gz
drm/i915: Read eDP Display control capability registers
Add new edp_dpcd variable to intel_dp. Read and save eDP Display control capability registers to edp_dpcd. Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459865452-9138-3-git-send-email-yetundex.adebisi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b9f1304..99db8bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -810,6 +810,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+ uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
uint8_t num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
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