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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-13 23:41:27 +0300 |
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committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-23 21:11:13 +0300 |
commit | b204535204fe9c1f647195ca587f210b18249904 (patch) | |
tree | caad8e1613676dd2bcf247e20da60a812b3de8e3 /drivers/gpu/drm/i915/intel_dpll_mgr.c | |
parent | 1cd593e009db55d5844056305309bb52639d71a8 (diff) | |
download | op-kernel-dev-b204535204fe9c1f647195ca587f210b18249904.zip op-kernel-dev-b204535204fe9c1f647195ca587f210b18249904.tar.gz |
drm/i915: Keep track of preferred cdclk vco frequency on SKL
Now that skl_vco_freq tracks the actual DPLL0 vco frequency, we'll need
something that keeps track of which vco frequency we want to use in case
the current vco is 0. This would be important across supend/resume since
we'll disable DPLL0 around those parts.
We'll also update our idea of max cdclk/dotclock when the preferred
vco changes. That could happen if out initial guess was wrong, and
later eDP would force us to change it. One issue here could be that
changing the max dotclock could cause our mode list to change during
next time the displays get probed. But I don't see a good way to avoid
that, except perhaps by allowing either vco frequency to be used as
needed. But the docs suggest that such usage wasn't really inteded.
Also need to make sure we don't update our max_cdclk value before we
have a preferred vco value, which means moving that to happen after
the cdclk sanitation.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-9-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpll_mgr.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dpll_mgr.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 5391ab6..34ec149 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1635,6 +1635,11 @@ static void intel_ddi_pll_init(struct drm_device *dev) if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { if (skl_sanitize_cdclk(dev_priv)) DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); + + /* We'll want to keep using the current vco from now on */ + if (dev_priv->skl_vco_freq != 0) + skl_set_preferred_cdclk_vco(dev_priv, + dev_priv->skl_vco_freq); } else if (!IS_BROXTON(dev_priv)) { /* * The LCPLL register should be turned on by the BIOS. For now |