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author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-12-02 10:23:52 +0200 |
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committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-12-02 16:41:35 +0200 |
commit | 51b3ee35affa3695bd89f6c6cdb22cd65aff5155 (patch) | |
tree | 2aba0aa37accc8309a4743ec932feac8a1463ed0 /drivers/gpu/drm/i915/intel_dpll_mgr.c | |
parent | 0a116ce895e7ee2831c6304df246c40a33bcf454 (diff) | |
download | op-kernel-dev-51b3ee35affa3695bd89f6c6cdb22cd65aff5155.zip op-kernel-dev-51b3ee35affa3695bd89f6c6cdb22cd65aff5155.tar.gz |
drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
Follow the PLL enable sequence updated in bspec, which requires the DCC
delay range 2 bit to be set.
v2: Moved from DDI init sequence to PLL enable.
v3: Don't read value from GRP register. (Rodrido)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-5-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpll_mgr.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 8a82507..63104b7 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1458,6 +1458,12 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 200)) DRM_ERROR("PLL %d not locked\n", port); + if (IS_GEMINILAKE(dev_priv)) { + temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch)); + temp |= DCC_DELAY_RANGE_2; + I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp); + } + /* * While we write to the group register to program all lanes at once we * can read only lane registers and we pick lanes 0/1 for that. |