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| author | Keith Packard <keithp@keithp.com> | 2011-09-19 13:54:47 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-09-30 16:23:45 -0700 |
| commit | 9b984daec45632c4c1ef6e628dca4d2bc8f544ed (patch) | |
| tree | 93dc57e7d712dcf1be291b078308894ce01c1bc5 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | 47f0eb2234a2a1c790825393bbaccfadf82463d3 (diff) | |
| download | op-kernel-dev-9b984daec45632c4c1ef6e628dca4d2bc8f544ed.zip op-kernel-dev-9b984daec45632c4c1ef6e628dca4d2bc8f544ed.tar.gz | |
drm/i915: Check eDP power when doing aux channel communications
Verify that the eDP VDD is on, either with the panel being on or with
the VDD force-on bit being set.
This demonstrates that in many instances, VDD is not on when needed,
which leads to failed EDID communications.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3717fa6..1bf3258 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -279,6 +279,24 @@ intel_hrawclk(struct drm_device *dev) } } +static void +intel_dp_check_edp(struct intel_dp *intel_dp) +{ + struct drm_device *dev = intel_dp->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 pp_status, pp_control; + if (!is_edp(intel_dp)) + return; + pp_status = I915_READ(PCH_PP_STATUS); + pp_control = I915_READ(PCH_PP_CONTROL); + if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) { + WARN(1, "eDP powered off while attempting aux channel communication.\n"); + DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", + pp_status, + I915_READ(PCH_PP_CONTROL)); + } +} + static int intel_dp_aux_ch(struct intel_dp *intel_dp, uint8_t *send, int send_bytes, @@ -295,6 +313,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, uint32_t aux_clock_divider; int try, precharge; + intel_dp_check_edp(intel_dp); /* The clock divider is based off the hrawclk, * and would like to run at 2MHz. So, take the * hrawclk value and divide by 2 and use that @@ -408,6 +427,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp, int msg_bytes; uint8_t ack; + intel_dp_check_edp(intel_dp); if (send_bytes > 16) return -1; msg[0] = AUX_NATIVE_WRITE << 4; @@ -450,6 +470,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp, uint8_t ack; int ret; + intel_dp_check_edp(intel_dp); msg[0] = AUX_NATIVE_READ << 4; msg[1] = address >> 8; msg[2] = address & 0xff; @@ -493,6 +514,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, int reply_bytes; int ret; + intel_dp_check_edp(intel_dp); /* Set up the command byte */ if (mode & MODE_I2C_READ) msg[0] = AUX_I2C_READ << 4; |
