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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-11 10:30:13 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-23 07:05:17 +0200 |
| commit | 3638379cfe83604f2759399a998fa90ad0fd56ca (patch) | |
| tree | 988708aea6704ef6c2d66a69da7eb0e667096813 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | e921bcbfba1f973c60e3c537adeb32e0cdf2eb77 (diff) | |
| download | op-kernel-dev-3638379cfe83604f2759399a998fa90ad0fd56ca.zip op-kernel-dev-3638379cfe83604f2759399a998fa90ad0fd56ca.tar.gz | |
drm/i915: Lock down psr sw/hw state tracking
Make sure we track the sw side (psr.active) correctly and WARN
everywhere it might get out of sync with the hw.
v2: Fixup WARN_ON logic inversion, reported by Rodrigo.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 43 |
1 files changed, 23 insertions, 20 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0184188..f630c23 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1834,8 +1834,8 @@ static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (intel_edp_is_psr_enabled(dev)) - return; + WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); + WARN_ON(dev_priv->psr.active); /* Enable PSR on the panel */ intel_edp_psr_enable_sink(intel_dp); @@ -1876,13 +1876,19 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp) if (!dev_priv->psr.enabled) return; - I915_WRITE(EDP_PSR_CTL(dev), - I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); + if (dev_priv->psr.active) { + I915_WRITE(EDP_PSR_CTL(dev), + I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); + + /* Wait till PSR is idle */ + if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & + EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) + DRM_ERROR("Timed out waiting for PSR Idle State\n"); - /* Wait till PSR is idle */ - if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & - EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) - DRM_ERROR("Timed out waiting for PSR Idle State\n"); + dev_priv->psr.active = false; + } else { + WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); + } dev_priv->psr.enabled = NULL; } @@ -1900,16 +1906,6 @@ static void intel_edp_psr_work(struct work_struct *work) intel_edp_psr_do_enable(intel_dp); } -static void intel_edp_psr_inactivate(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - dev_priv->psr.active = false; - - I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev)) - & ~EDP_PSR_ENABLE); -} - void intel_edp_psr_exit(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -1922,8 +1918,15 @@ void intel_edp_psr_exit(struct drm_device *dev) cancel_delayed_work_sync(&dev_priv->psr.work); - if (dev_priv->psr.active) - intel_edp_psr_inactivate(dev); + if (dev_priv->psr.active) { + u32 val = I915_READ(EDP_PSR_CTL(dev)); + + WARN_ON(!(val & EDP_PSR_ENABLE)); + + I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); + + dev_priv->psr.active = false; + } schedule_delayed_work(&dev_priv->psr.work, msecs_to_jiffies(100)); |
