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authorJani Nikula <jani.nikula@intel.com>2017-04-06 16:44:12 +0300
committerJani Nikula <jani.nikula@intel.com>2017-04-11 16:54:31 +0300
commite6c0c64a291e20e34668b8878b34af78389f9da3 (patch)
treebe64db0b96a72e621431a55086b2ddda2b470f1b /drivers/gpu/drm/i915/intel_dp.c
parentb1810a74a0513993e02ba13e60a29c5f01ea3bf0 (diff)
downloadop-kernel-dev-e6c0c64a291e20e34668b8878b34af78389f9da3.zip
op-kernel-dev-e6c0c64a291e20e34668b8878b34af78389f9da3.tar.gz
drm/i915/dp: don't call the link parameters sink parameters
If we modify these on the fly depending on the link conditions, don't pretend they are sink properties. Some link vs. sink confusion still remains, but we'll take care of them in follow-up patches. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/3739b4fac502ebd1c6e075a62c1a195e4094eb16.1491485983.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8c061c5..a0082a3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -172,7 +172,7 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
u8 source_max, sink_max;
source_max = intel_dig_port->max_lanes;
- sink_max = intel_dp->max_sink_lane_count;
+ sink_max = intel_dp->max_link_lane_count;
return min(source_max, sink_max);
}
@@ -326,11 +326,11 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
intel_dp->num_common_rates,
link_rate);
if (index > 0) {
- intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1];
- intel_dp->max_sink_lane_count = lane_count;
+ intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
+ intel_dp->max_link_lane_count = lane_count;
} else if (lane_count > 1) {
- intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
- intel_dp->max_sink_lane_count = lane_count >> 1;
+ intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
+ intel_dp->max_link_lane_count = lane_count >> 1;
} else {
DRM_ERROR("Link Training Unsuccessful\n");
return -1;
@@ -1561,8 +1561,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
int len;
- len = intel_dp_common_len_rate_limit(intel_dp,
- intel_dp->max_sink_link_rate);
+ len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
if (WARN_ON(len <= 0))
return 162000;
@@ -1639,7 +1638,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
uint8_t link_bw, rate_select;
common_len = intel_dp_common_len_rate_limit(intel_dp,
- intel_dp->max_sink_link_rate);
+ intel_dp->max_link_rate);
/* No common link rates between source and sink */
WARN_ON(common_len <= 0);
@@ -3969,7 +3968,7 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
test_lane_count &= DP_MAX_LANE_COUNT_MASK;
/* Validate the requested lane count */
if (test_lane_count < min_lane_count ||
- test_lane_count > intel_dp->max_sink_lane_count)
+ test_lane_count > intel_dp->max_link_lane_count)
return DP_TEST_NAK;
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
@@ -4637,11 +4636,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
if (intel_dp->reset_link_params) {
- /* Set the max lane count for sink */
- intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ /* Set the max lane count for link */
+ intel_dp->max_link_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
- /* Set the max link rate for sink */
- intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
+ /* Set the max link rate for link */
+ intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
intel_dp->reset_link_params = false;
}
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