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authorChris Wilson <chris@chris-wilson.co.uk>2010-07-05 18:01:46 +0100
committerEric Anholt <eric@anholt.net>2010-08-01 19:03:47 -0700
commit534843dabf79da40561148764916e1b2e6bbcebe (patch)
tree1871363e1e220e2645726d6aa5144be5511ef7f5 /drivers/gpu/drm/i915/intel_display.c
parente1a4474349997d722e4ae64e40a68feb25307109 (diff)
downloadop-kernel-dev-534843dabf79da40561148764916e1b2e6bbcebe.zip
op-kernel-dev-534843dabf79da40561148764916e1b2e6bbcebe.tar.gz
drm/i915: Use 128k alignment for untiled display surface on i965 (v2)
The original i965, including the revised G35 and Q35, requires an alignment of 128K for the display surface with linear memory, so increase the requirement from 64k for these chipsets. For the later chipsets in the i965 family, only a 4k alignment is required. (So long as we do not start performing asynchronous flips.) Note the impact of this should be slight as on i965 we should be using a tiled frontbuffer for anything up to a 4096x4096 display. v2: compilation fixes and note that the docs do not exclude the G35 from the extra alignment. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f67c74a..8359c50 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1329,7 +1329,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
switch (obj_priv->tiling_mode) {
case I915_TILING_NONE:
- alignment = 64 * 1024;
+ if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+ alignment = 128 * 1024;
+ else if (IS_I965G(dev))
+ alignment = 4 * 1024;
+ else
+ alignment = 64 * 1024;
break;
case I915_TILING_X:
/* pin() will align the object as required by fence */
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