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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-09-30 17:06:43 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-10-01 18:12:16 +0200 |
| commit | 923c124107840d58c5002cc19734310743501811 (patch) | |
| tree | cd87402e407f7a15c9ee40a4ce9fefb6cc175d00 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | 76305b1a68e196c4f76d15ec1897097bb7a7c641 (diff) | |
| download | op-kernel-dev-923c124107840d58c5002cc19734310743501811.zip op-kernel-dev-923c124107840d58c5002cc19734310743501811.tar.gz | |
drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.
v2: Use SKL_DPLLx symbolic names instead of raw numbers
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 9c11577..2d3cc82 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -969,8 +969,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, uint32_t cfgcr1_val, cfgcr2_val; uint32_t p0, p1, p2, dco_freq; - cfgcr1_reg = GET_CFG_CR1_REG(dpll); - cfgcr2_reg = GET_CFG_CR2_REG(dpll); + cfgcr1_reg = DPLL_CFGCR1(dpll); + cfgcr2_reg = DPLL_CFGCR2(dpll); cfgcr1_val = I915_READ(cfgcr1_reg); cfgcr2_val = I915_READ(cfgcr2_reg); @@ -2504,20 +2504,20 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = { { /* DPLL 1 */ .ctl = LCPLL2_CTL, - .cfgcr1 = DPLL1_CFGCR1, - .cfgcr2 = DPLL1_CFGCR2, + .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), + .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), }, { /* DPLL 2 */ .ctl = WRPLL_CTL1, - .cfgcr1 = DPLL2_CFGCR1, - .cfgcr2 = DPLL2_CFGCR2, + .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), + .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), }, { /* DPLL 3 */ .ctl = WRPLL_CTL2, - .cfgcr1 = DPLL3_CFGCR1, - .cfgcr2 = DPLL3_CFGCR2, + .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), + .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), }, }; |
