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authorLu, Han <han.lu@intel.com>2015-05-05 09:05:47 +0800
committerTakashi Iwai <tiwai@suse.de>2015-05-05 14:44:19 +0200
commit632f3ab95fe2ffebf09969a57ab21be409ed7dcc (patch)
tree0db6c403b6d893bb1e831397df5fa48bc65171b4 /drivers/gpu/drm/i915/intel_audio.c
parentbd5b2d440745707ee97159ed7a06b629760fd19b (diff)
downloadop-kernel-dev-632f3ab95fe2ffebf09969a57ab21be409ed7dcc.zip
op-kernel-dev-632f3ab95fe2ffebf09969a57ab21be409ed7dcc.tar.gz
drm/i915/audio: add codec wakeup override enabled/disable callback
Add support for enabling codec wakeup override signal to allow re-enumeration of the controller on SKL after resume from low power state. In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power wells, so it's necessary to reset display audio codecs when power well on, otherwise display audio codecs will disappear when resume from low power state. Reset steps when power on: enable codec wakeup -> azx_init_chip() -> disable codec wakeup v3 by Jani: Simplify to only support toggling the appropriate chicken bit. v4 by Han: add explanation and specify the hw swquence. Signed-off-by: Lu, Han <han.lu@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_audio.c')
-rw-r--r--drivers/gpu/drm/i915/intel_audio.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 2396cc7..ef34257 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -475,6 +475,32 @@ static void i915_audio_component_put_power(struct device *dev)
intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
}
+static void i915_audio_component_codec_wake_override(struct device *dev,
+ bool enable)
+{
+ struct drm_i915_private *dev_priv = dev_to_i915(dev);
+ u32 tmp;
+
+ if (!IS_SKYLAKE(dev_priv))
+ return;
+
+ /*
+ * Enable/disable generating the codec wake signal, overriding the
+ * internal logic to generate the codec wake to controller.
+ */
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+
+ if (enable) {
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+ }
+}
+
/* Get CDCLK in kHz */
static int i915_audio_component_get_cdclk_freq(struct device *dev)
{
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops i915_audio_component_ops = {
.owner = THIS_MODULE,
.get_power = i915_audio_component_get_power,
.put_power = i915_audio_component_put_power,
+ .codec_wake_override = i915_audio_component_codec_wake_override,
.get_cdclk_freq = i915_audio_component_get_cdclk_freq,
};
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