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authorJani Nikula <jani.nikula@intel.com>2014-10-27 16:27:00 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-07 18:42:19 +0100
commit28855d2ac349b3fbb285c38493429dd1aa503523 (patch)
tree2748c3717f14023f36b9fcb3a40f21cdbbb9895f /drivers/gpu/drm/i915/intel_audio.c
parent82910ac6d575d4ce4bd4dcefb61923623b263e00 (diff)
downloadop-kernel-dev-28855d2ac349b3fbb285c38493429dd1aa503523.zip
op-kernel-dev-28855d2ac349b3fbb285c38493429dd1aa503523.tar.gz
drm/i915/audio: add DOC comment describing HDA over HDMI/DP
v2: include the section in the drm docbook. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_audio.c')
-rw-r--r--drivers/gpu/drm/i915/intel_audio.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 9181b85d..44c49df 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -28,6 +28,27 @@
#include "intel_drv.h"
#include "i915_drv.h"
+/**
+ * DOC: High Definition Audio over HDMI and Display Port
+ *
+ * The graphics and audio drivers together support High Definition Audio over
+ * HDMI and Display Port. The audio programming sequences are divided into audio
+ * codec and controller enable and disable sequences. The graphics driver
+ * handles the audio codec sequences, while the audio driver handles the audio
+ * controller sequences.
+ *
+ * The disable sequences must be performed before disabling the transcoder or
+ * port. The enable sequences may only be performed after enabling the
+ * transcoder and port, and after completed link training.
+ *
+ * The codec and controller sequences could be done either parallel or serial,
+ * but generally the ELDV/PD change in the codec sequence indicates to the audio
+ * driver that the controller sequence should start. Indeed, most of the
+ * co-operation between the graphics and audio drivers is handled via audio
+ * related registers. (The notable exception is the power management, not
+ * covered here.)
+ */
+
static const struct {
int clock;
u32 config;
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