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| author | Michel Thierry <michel.thierry@intel.com> | 2015-08-03 09:52:01 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-08-14 18:16:20 +0200 |
| commit | 81ba8aefd03803a8aec3395d18f7b1dda5942105 (patch) | |
| tree | f61a2d6f5f74c1bbfffbdcbdbe3bd1af0f6cbfda /drivers/gpu/drm/i915/i915_trace.h | |
| parent | 4c06ec8d13d2b0e57479bb135e49afd56ebe9275 (diff) | |
| download | op-kernel-dev-81ba8aefd03803a8aec3395d18f7b1dda5942105.zip op-kernel-dev-81ba8aefd03803a8aec3395d18f7b1dda5942105.tar.gz | |
drm/i915/gen8: Add PML4 structure
Introduces the Page Map Level 4 (PML4), ie. the new top level structure
of the page tables.
To facilitate testing, 48b mode will be available on Broadwell and
GEN9+, when i915.enable_ppgtt = 3.
v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt code is already
32/64-bit safe (Chris).
v3: Add goto free_scratch in temp 48-bit mode init code (Akash).
v4: kfree the pdp until the 4lvl alloc/free patch (Akash).
v5: Postpone 48-bit code in sanitize_enable_ppgtt (Akash).
v6: Keep _insert_pte_entries changes outside this patch (Akash).
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_trace.h')
0 files changed, 0 insertions, 0 deletions
