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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-03-31 11:21:57 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-11 12:16:53 +0200 |
| commit | 80e829fade4eea5f07c410df6a551c42e2d0ca9c (patch) | |
| tree | c347937e2a2d83b0e9154b33866a0bfdc99251b3 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 27c1cbd06a7620b354cbb363834f3bb8df4f410d (diff) | |
| download | op-kernel-dev-80e829fade4eea5f07c410df6a551c42e2d0ca9c.zip op-kernel-dev-80e829fade4eea5f07c410df6a551c42e2d0ca9c.tar.gz | |
drm/i915: implement ColorBlt w/a
According to an internal workaround master list, we need to set bit 5
of register 9400 to avoid issues with color blits.
Testing shows that this seems to fix the blitter hangs when fbc is
enabled on snb, thanks to Chris Wilson for figuring this out.
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Michael "brot" Groh <michael.groh@minad.de>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2abf4eb..b4bb1ef 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3728,6 +3728,9 @@ #define GT_FIFO_FREE_ENTRIES 0x120008 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 +#define GEN6_UCGCTL1 0x9400 +# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) + #define GEN6_UCGCTL2 0x9404 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
