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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-05-21 21:56:13 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-06-01 18:40:19 +0300 |
| commit | 0a59952b24e24e153b8d1cbd781c8d264257b1b3 (patch) | |
| tree | b5bc1c4fcec43611ff681981e465bd9873c458cc /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 012d79e6a33f095c293fe2a02b2b3b26d8c6402c (diff) | |
| download | op-kernel-dev-0a59952b24e24e153b8d1cbd781c8d264257b1b3.zip op-kernel-dev-0a59952b24e24e153b8d1cbd781c8d264257b1b3.tar.gz | |
drm/i915: Configure SKL+ scaler initial phase correctly
Set up the SKL+ scaler initial phase registers correctly. Otherwise
we start fetching the data from the center of the first pixel instead
of the top-left corner, which obviously then leads to right/bottom edges
replicating data excessively as the data runs out half a pixel too soon.
Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180521185613.5097-2-ville.syrjala@linux.intel.com
Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 749d238..43397e5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6789,6 +6789,10 @@ enum { #define _PS_VPHASE_1B 0x68988 #define _PS_VPHASE_2B 0x68A88 #define _PS_VPHASE_1C 0x69188 +#define PS_Y_PHASE(x) ((x) << 16) +#define PS_UV_RGB_PHASE(x) ((x) << 0) +#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ +#define PS_PHASE_TRIP (1 << 0) #define _PS_HPHASE_1A 0x68194 #define _PS_HPHASE_2A 0x68294 |
