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authorIngo Molnar <mingo@elte.hu>2008-12-12 13:48:57 +0100
committerIngo Molnar <mingo@elte.hu>2008-12-12 13:48:57 +0100
commit45ab6b0c76d0e4cce5bd608ccf97b0f6b20f18df (patch)
tree4d51c73533c386aee16fde1e74b5e3bc22eedc53 /drivers/gpu/drm/i915/i915_reg.h
parent81444a799550214f549caf579cf65a0ca55e70b7 (diff)
parentd65bd5ecb2bd166cea4952a59b7e16cc3ad6ef6c (diff)
downloadop-kernel-dev-45ab6b0c76d0e4cce5bd608ccf97b0f6b20f18df.zip
op-kernel-dev-45ab6b0c76d0e4cce5bd608ccf97b0f6b20f18df.tar.gz
Merge branch 'sched/core' into cpus4096
Conflicts: include/linux/ftrace.h kernel/sched.c
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e476eb..9d24aae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -522,6 +522,7 @@
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
#define DCC_ADDRESSING_MODE_MASK (3 << 0)
#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
+#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
/** 965 MCH register controlling DRAM channel configuration */
#define C0DRB3 0x10206
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