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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-07-05 12:17:30 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-07-05 13:36:01 +0200 |
| commit | c2c75131244507c93f812862fdbd4f3a37139401 (patch) | |
| tree | 068e1aae4099aafe1a31948e382bf882af43d378 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | e506a0c6381f180858d2e343c3ed5c0bde8e84ba (diff) | |
| download | op-kernel-dev-c2c75131244507c93f812862fdbd4f3a37139401.zip op-kernel-dev-c2c75131244507c93f812862fdbd4f3a37139401.tar.gz | |
drm/i915: adjust framebuffer base address on gen4+
The tileoffset register only supports a limited offset in x/y of 4096,
so for giant screen configuration with a shared fb we wrap around.
Fix this by computing a linear offset in tiles (pages) and only use
the tileoffset register to offset within the tile.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4a2ea42..da7484e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2986,7 +2986,7 @@ #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ - (I915_WRITE(reg, gfx_addr | I915_LO_DISPBASE(I915_READ(reg)))) + (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) /* VBIOS flags */ #define SWF00 0x71410 |
