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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-04-28 14:15:24 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-05-20 15:43:18 +0200 |
| commit | d2152b2524a96e6cb71097ea26c2e7c3f9e3ee12 (patch) | |
| tree | ecd005705a3389ff03ae2510283e0c37b837306b /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 580d3811f4465feee9d5cacdc88b6aa6b345eff5 (diff) | |
| download | op-kernel-dev-d2152b2524a96e6cb71097ea26c2e7c3f9e3ee12.zip op-kernel-dev-d2152b2524a96e6cb71097ea26c2e7c3f9e3ee12.tar.gz | |
drm/i915/chv: Set soft reset override bit for data lane resets
The bits we've been setting so far only progagate the reset singal to
the data lanes. To actaully force the reset signal we need to set another
override bit.
v2: Fix mispalced ';' (Mika)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1ae55fc..5d1d287 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -661,6 +661,7 @@ enum punit_power_well { #define _VLV_PCS_DW1_CH0 0x8204 #define _VLV_PCS_DW1_CH1 0x8404 +#define CHV_PCS_REQ_SOFTRESET_EN (1<<23) #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
