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author | Shashank Sharma <shashank.sharma@intel.com> | 2014-05-19 20:54:03 +0530 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-05-19 17:56:40 +0200 |
commit | b6fdd0f2b990006daba19eec676b632faa523fc8 (patch) | |
tree | c984efc772cb0cc0cfd210e84cea6f232a5ecba3 /drivers/gpu/drm/i915/i915_reg.h | |
parent | eed6d67d9284f62aa19857564882017e4670d31c (diff) | |
download | op-kernel-dev-b6fdd0f2b990006daba19eec676b632faa523fc8.zip op-kernel-dev-b6fdd0f2b990006daba19eec676b632faa523fc8.tar.gz |
drm/i915: Add MIPI mmio reg base
This patch adds a mmio base address variable for DSI display,
to make the DSI code generic, so that, if required, the same code
can be re-used for future platforms with different mmio base.
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Appease checkpatch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3d437d1..2a4aac4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1032,6 +1032,7 @@ enum punit_power_well { #define GFX_PPGTT_ENABLE (1<<9) #define VLV_DISPLAY_BASE 0x180000 +#define VLV_MIPI_BASE VLV_DISPLAY_BASE #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) |