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| author | Deepak S <deepak.s@linux.intel.com> | 2014-07-10 13:16:24 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-11 18:22:00 +0200 |
| commit | 67c3bf6f55a97a0915a0f9ea07278a3073cc9601 (patch) | |
| tree | efed3f9d8cc82c764e60f0401b5f74b30c8cd55b /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 74c4f62bcdbb0e2ee115197eafd4edc05bbcf55c (diff) | |
| download | op-kernel-dev-67c3bf6f55a97a0915a0f9ea07278a3073cc9601.zip op-kernel-dev-67c3bf6f55a97a0915a0f9ea07278a3073cc9601.tar.gz | |
drm/i915: populate mem_freq/cz_clock for chv
We need mem_freq or cz clock for freq/opcode conversion
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2d2c4de..0ebe0f4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5538,6 +5538,12 @@ enum punit_power_well { GEN6_PM_RP_DOWN_THRESHOLD | \ GEN6_PM_RP_DOWN_TIMEOUT) +#define CHV_CZ_CLOCK_FREQ_MODE_200 200 +#define CHV_CZ_CLOCK_FREQ_MODE_267 267 +#define CHV_CZ_CLOCK_FREQ_MODE_320 320 +#define CHV_CZ_CLOCK_FREQ_MODE_333 333 +#define CHV_CZ_CLOCK_FREQ_MODE_400 400 + #define GEN7_GT_SCRATCH_BASE 0x4F100 #define GEN7_GT_SCRATCH_REG_NUM 8 |
