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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-29 16:07:51 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-30 21:57:10 -0700 |
| commit | 86ebb015fa744dd1e265c9b45ade870ac859a4d5 (patch) | |
| tree | 0a1617abc5f70bfe530c9e68b911e8c07a64999a /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 392572feb01c03c9db2f73993bdbff2b5ed45c38 (diff) | |
| download | op-kernel-dev-86ebb015fa744dd1e265c9b45ade870ac859a4d5.zip op-kernel-dev-86ebb015fa744dd1e265c9b45ade870ac859a4d5.tar.gz | |
drm/i915/cnl: WaDisableI2mCycleOnWRPort
On CNL B0 stepping GAM is not able to detect some deadlock
condition and then rise the rise the gam_coh_flush.
WA database and spec both mentions to set 4AB8[24]=1 as
workaround. Although register offset 0x4AB8 is not
documented for any platform.
References: HSD#1945815, BSID#1112
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829230751.21047-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1ad22a8..c718c2f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2373,6 +2373,7 @@ enum i915_power_well_id { #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28) +#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24) #if 0 #define PRB0_TAIL _MMIO(0x2030) |
