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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-02-14 17:07:09 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-02-14 20:32:29 +0100 |
| commit | 7c26e5c6edaec70f12984f7a3020864cc21e6fec (patch) | |
| tree | 0221d3a6583684c447e516cf356361a721246ac9 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 8a8ed1f5143b3df312e436ab15290e4a7ca6a559 (diff) | |
| download | op-kernel-dev-7c26e5c6edaec70f12984f7a3020864cc21e6fec.zip op-kernel-dev-7c26e5c6edaec70f12984f7a3020864cc21e6fec.tar.gz | |
drm/i915: add missing SDVO bits for interlaced modes on ILK
This was pointed by Jesse Barnes. The code now seems to follow the
specification but I don't have an SDVO device to really test this.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5c62b78..52a06be 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3365,6 +3365,7 @@ #define TRANS_INTERLACE_MASK (7<<21) #define TRANS_PROGRESSIVE (0<<21) #define TRANS_INTERLACED (3<<21) +#define TRANS_LEGACY_INTERLACED_ILK (2<<21) #define TRANS_8BPC (0<<5) #define TRANS_10BPC (1<<5) #define TRANS_6BPC (2<<5) |
