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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-29 16:07:23 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-30 21:56:06 -0700 |
| commit | 392572feb01c03c9db2f73993bdbff2b5ed45c38 (patch) | |
| tree | 3f204f92cca23c2820448a4edbc6bf65c54e53ad /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 91200c09d38bbc959671b91f5801d1016b409969 (diff) | |
| download | op-kernel-dev-392572feb01c03c9db2f73993bdbff2b5ed45c38.zip op-kernel-dev-392572feb01c03c9db2f73993bdbff2b5ed45c38.tar.gz | |
drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
WA to enable HW L1 Banking fix that allows aniso to operate
at full sample rate.
References: HSD#1937670
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829230723.20898-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2908ae..1ad22a8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8072,6 +8072,7 @@ enum { #define HSW_SAMPLE_C_PERFORMANCE (1<<9) #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) +#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4) #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) |
