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authorDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>2017-09-08 17:42:55 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2017-09-12 10:33:16 -0700
commit4ebc65092ca3d9713d48ea43e7db5b3f07faf1bc (patch)
treea027e62a9225a16d49d9f0368628712eb5ef1d3c /drivers/gpu/drm/i915/i915_irq.c
parent61843f0e6212a8592cba26ff554af4af0dd93778 (diff)
downloadop-kernel-dev-4ebc65092ca3d9713d48ea43e7db5b3f07faf1bc.zip
op-kernel-dev-4ebc65092ca3d9713d48ea43e7db5b3f07faf1bc.tar.gz
drm/i915/spt+: Don't reset invalid AUX channel interrupt bits in SDEIMR
The SDE interrupt bits 25, 26 and 27 are either reserved or meant for DDI E hotplug in SPT+. These bits are meant for AUX channels only in LPT and CPT, so add the appropriate checks. Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170909004255.14827-1-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e6..91a2c5d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3241,8 +3241,10 @@ static void ibx_irq_postinstall(struct drm_device *dev)
if (HAS_PCH_IBX(dev_priv))
mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
- else
+ else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
+ else
+ mask = SDE_GMBUS_CPT;
gen5_assert_iir_is_zero(dev_priv, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
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