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authorChris Wilson <chris@chris-wilson.co.uk>2017-03-09 21:12:31 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2017-03-10 14:28:44 +0000
commit569884e3d47d54d943c13eb14d653a6100937f14 (patch)
treeb46938c28a6314683e88dcaf7e6b67b40985eefd /drivers/gpu/drm/i915/i915_irq.c
parente0e8c7cb6eb68e9256de2d8cbeb481d3701c05ac (diff)
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op-kernel-dev-569884e3d47d54d943c13eb14d653a6100937f14.tar.gz
drm/i915: Use max(render, media) for Baytrail busyness calculation
Currently, we sum the render and media cycles (on different engines) to compute a percentage - but we fail to factor in the duplication into the threshold calculations. This makes us very eager to upclock! If we just consider the maximum busy cycles of either counter, we should have an accurate reflection on whether there are cycles to spare to handle the workload at this frequency. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170309211232.28878-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2316261..4469cac 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1102,6 +1102,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
if (prev->cz_clock) {
u64 time, c0;
+ u32 render, media;
unsigned int mul;
mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
@@ -1116,8 +1117,9 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
* mesa. To account for this we need to combine both engines
* into our activity counter.
*/
- c0 = now.render_c0 - prev->render_c0;
- c0 += now.media_c0 - prev->media_c0;
+ render = now.render_c0 - prev->render_c0;
+ media = now.media_c0 - prev->media_c0;
+ c0 = max(render, media);
c0 *= mul;
if (c0 > time * dev_priv->rps.up_threshold)
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