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author | Ben Widawsky <benjamin.widawsky@intel.com> | 2014-01-30 00:19:40 -0800 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-01-30 13:01:02 +0100 |
commit | 6c7a01ec3743a5a6ce9e53a69d7a6c2d8c715eb1 (patch) | |
tree | 6a89d2028d1f7fc87915902bdf018e767a86ad6e /drivers/gpu/drm/i915/i915_gpu_error.c | |
parent | 91ec5d11ab6fea7eafd0364b77cd39baf60cd8e3 (diff) | |
download | op-kernel-dev-6c7a01ec3743a5a6ce9e53a69d7a6c2d8c715eb1.zip op-kernel-dev-6c7a01ec3743a5a6ce9e53a69d7a6c2d8c715eb1.tar.gz |
drm/i915: Capture PPGTT info on error capture
v2: Rebased upon cleaned up error state
v3: Make sure hangcheck info remains last (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gpu_error.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gpu_error.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 70a7cd7..094995f 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -270,6 +270,19 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m, ring->semaphore_seqno[2]); } } + if (USES_PPGTT(dev)) { + err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); + + if (INTEL_INFO(dev)->gen >= 8) { + int i; + for (i = 0; i < 4; i++) + err_printf(m, " PDP%d: 0x%016llx\n", + i, ring->vm_info.pdp[i]); + } else { + err_printf(m, " PP_DIR_BASE: 0x%08x\n", + ring->vm_info.pp_dir_base); + } + } err_printf(m, " seqno: 0x%08x\n", ring->seqno); err_printf(m, " waiting: %s\n", yesno(ring->waiting)); err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); @@ -835,6 +848,30 @@ static void i915_record_ring_state(struct drm_device *dev, ering->hangcheck_score = ring->hangcheck.score; ering->hangcheck_action = ring->hangcheck.action; + + if (USES_PPGTT(dev)) { + int i; + + ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); + + switch (INTEL_INFO(dev)->gen) { + case 8: + for (i = 0; i < 4; i++) { + ering->vm_info.pdp[i] = + I915_READ(GEN8_RING_PDP_UDW(ring, i)); + ering->vm_info.pdp[i] <<= 32; + ering->vm_info.pdp[i] |= + I915_READ(GEN8_RING_PDP_LDW(ring, i)); + } + break; + case 7: + ering->vm_info.pp_dir_base = RING_PP_DIR_BASE(ring); + break; + case 6: + ering->vm_info.pp_dir_base = RING_PP_DIR_BASE_READ(ring); + break; + } + } } |