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| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-05-10 10:57:06 +0100 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-05-11 12:27:27 +0100 |
| commit | 7e22dbbbae81bfdf26b468aaa1c9a9570f7476ba (patch) | |
| tree | 9e6cb09c120d1658e07c4a1deaae613cdb3d8fcc /drivers/gpu/drm/i915/i915_gem_tiling.c | |
| parent | ab0d24ac38e34c03a6ced9b9c458a07ab3d431ea (diff) | |
| download | op-kernel-dev-7e22dbbbae81bfdf26b468aaa1c9a9570f7476ba.zip op-kernel-dev-7e22dbbbae81bfdf26b468aaa1c9a9570f7476ba.tar.gz | |
drm/i915: Replace "INTEL_INFO->gen == x" checks with IS_GENx
This way optimization from a previous patch works even better.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 829dab6..2fcb4af 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -125,7 +125,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) if (INTEL_INFO(obj->base.dev)->gen >= 4) return true; - if (INTEL_INFO(obj->base.dev)->gen == 3) { + if (IS_GEN3(obj->base.dev)) { if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) return false; } else { |
